Role Summary
As a senior member of the SOC Verification team, you will lead a team of verification engineers and verify new breeds of SoC for advanced perception applications utilizing 4-D Lidar. You will architect and develop verification environments for block, subsystem, and full-chip using state-of-art verification techniques, and verify complex SoC designs.
What you'll be doing:
Lead and drive block, subsystems, and full-chip verification of advanced ARM-based SOCs. Architect and build test benches, reference models, and scoreboards using SystemVerilog and UVM-constrained random methodologies Define and execute test plan for block, subsystem, and full-chip using SV/UVM and C/C++ FW running on the on-chip ARM processors Work in a dynamic and fast-paced startup environment and work closely with a team of passionate engineers to define and enhance the processes, methodology, and tools to verify complex SoCs.Work with Architects, design and verification, and system software teams to define system-level verification plans and prove that SOC meets the functional, performance, and power target defined in the architecture and design specs. Identify and write functional coverage groups to improve test/stimulus qualityThrough coverage, analysis to identify verification gaps and achieve 100% coverage closureWork with the different stakeholders and cross-functional leads to ensure high-quality SoC delivery on timeWhat you'll have:
10+ years of experience in design, verification, and validation of advanced ARM based SOCs5+ years in architecting and building constrained random verification environments, reference models, scoreboards, and directed self-checking tests using SystemVerilog and UVM methodologiesDeep understanding of ARM-based SOC verification. Writing assembly and C/C++ diagnostic firmware for embedded ARM processors and debugging in a simulation environmentWorking experience and knowledge in AMBA protocols, CoreSight Debugger, LPDDR, Ethernet, MIPI, and high-speed serdes, etc.Solid programming skills in SystemVerilog, UVM, C/C++, assembly, Perl/Python.Proficient in debugging complex SOC or CPU core designsExcellent verbal and written communication skillsAbility to collaborate deeply with cross-functional leads and management teamsAbility to deliver results in a very fast-moving environmentDesire to learn & implement groundbreaking new processes and methodology for continuous verification improvement Nice to haves:
Diagnostics Firmware development and validation Experience in pre-silicon validation on emulation platforms such as Cadence Palladium, Mentor Veloce, Synopsys Zebu Post-silicon bring-up and validation planning and execution
