The Verification Engineer will define verification architecture, implement verification environment for block level, SoC subsystems and SOC top level design that use advance verification methodologies and meet established content, performance, quality, cost and schedule goals. He/She will also be responsible for the simulations of the SOC
Responsibilities
Define overall verification strategies, methodologies, and simulation environmentWork with RTL designers, system architects and block level verification engineers to develop top level verification requirements and test plans based on specifications.Develop, maintain and publish verification specifications.Analyze and debug simulation failuresGenerates code coverage and functional coverage reportRun gate level simulation and debug them.Perform the constraint assertion-based verificationQualifications and Skills
BS in EE with 3+ years of experience or MS in EE with 1+ year experienceStrong knowledge with ASIC Simulation Tool & Verification Language: all sign-off simulators, Verdi/SilotiFluent in verification language such as UVM/OVM/System Verilog, Vera, VerilogExperience in writing Test-plans and creating directed and random test casesStrong scripting skills in Perl, Python, Linux shells etc.
